1. Field of the Invention
The present invention generally relates to integrated circuit chip testers and more particularly to a universal banking box of switches that allow products to be tested on testers with fewer tester channels a product under test has pins.
2. Background of Invention
A product-design-specific Test Manufacturing Data (TMD) file is required for each ASIC logic product design. Since the TMD file is design-specific, creation of this file is typically the customers responsibility (some manufacturers offer Test Generation as a design service for ASIC customers). The TMD file contains a number of design-specific elements, including a complete gate-level logic model of the design and all the design-specific test patterns required to verify correct fabrication of the design.
For some ASIC products, the TMD contains reduced pin count test (RPCT) patterns for the logic circuitry, cores, and embedded memory that are internal to a boundary scan chain. These test patterns use a reduced number of product pins, called test I/O, that allow these internal tests to be applied using a low pin count tester. The TMD also includes an explicit external I/O test pattern subset that is used to test the logical and parametric functionality of the off-chip driver and receiver circuits that fall outside of the logical enclosure created by the boundary scan logic structure. These external I/O test patterns are generated under the assumption that all of the products signal I/O pins will be simultaneously contacted during test. This assumes the external I/O test patterns will be applied by a full pin count tester with as many test channels as the product has signal I/O pins. Although the internal tests can be applied with a low pin count tester, this assumes the external I/O tests would still require the high pin count tester.
The number of test channels on the tester has a direct relationship on the cost of Automatic Test Equipment (ATE). As an example, the International Technology Roadmap for Semiconductors (ITRS) estimates the cost of each reduced function (DC) tester channel to be $200. Adding 2048 DC channels to a RPCT tester would increase its cost by $409,600. Presently, when products have pin counts and volumes that exceed the capacity of existing testers, expensive higher pin count testers must be purchased. Future technology offerings will lead to products with even higher pin counts.